Doubt clarification regarding vhdl.

How do fgpa synthesizer interprets std_logic and synthesize them(in vhdl SYNTHESIS TOOL)?
can conditional and iterative statements be placed in programs without process?

std_logic is interpreted as binary '0' and '1'. The 7 other states are really only for simulation.

VHDL has no programs - so I dont really know what you're refering to.

You have conditional and selected signal assignments and generate loops in concurrent code.

If we cannot synthesize them why should we test them through simulation'
can if statement be used without process?

can if statement be used without process

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No. Time to read a VHDL tutorial or get you a text book.

Y.SAI SARASWATHI said:

If we cannot synthesize them why should we test them through simulation'
can if statement be used without process?

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Because they are useful. The other states are things like 'U' (uninitialised), 'X' (unknown, occurs when two signals drive the same signal, or can be used to detect bugs by forcing unknown in illegal states), 'Z' (high impedance - not used internall in an FPGA but needed for busses), '-' (dont care)

The other states are for digital logic outside of an FPGA ('H', 'L', 'W') on a PCB. VHDL was designed to model circuits, and in the mid 80s when it was designed, those circuits were more PCB oriented.

Y.SAI SARASWATHI said:

If we cannot synthesize them why should we test them through simulation'

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You use the other states of std_logic in order to allow a single simulation run to test all possible power up conditions. Depending on the specifics of the device, not every storage element inside powers up in the same state every time. So while you know the device will power up with a '0' or a '1', you don't know which one. This corresponds to std_logic's 'X' state.

Even if the device powers up in a known state (say '0'), you don't know that your code correctly handles this condition. You might have code that implicitly assumes a power up state of '1' and if it powers up as '0' your design doesn't work. Well, in the real device then it wouldn't work because it powers up as '0'.

It is rather difficult to root out the implicit assumptions by code inspection, but relatively straightforward in simulation with std_logic. If something gets initialized to 'X', it will propagate to whatever logic it drives. By designing so that the 'X' states do get driven by the design into the correct '0' or '1' prior to that signal being used then you've hardened the design so that no matter what the power up state, your design will work.

Although some say 'X' doesn't occur, it really does. 'X' means you don't know, it is not some mysterious third logic level of Boolean. Since one doesn't always know power up states, the other states of std_logic are testable in simulation and necessary from a design perspective to verify a design.

Kevin Jennings

How vhdl code can be used for automation of fgpa routing?(i,e how fgpa's are programmed using vhdl) so confused help me.

I'd say you're confused...so here are the highlights of FPGA design.

Step 1: Write or get a design specification
Step 2: Write vhdl code that implements the specification
Step 3: Write a testbench and run simulations until the design meets the requirements called out in the specification
Step 4: Create timing and placement constraints for the design so it will meet the requirements called out in the specification
Step 5: Synthesize the design in your vendor's tool (Xilinx - Vivado|ISE, Altera - Quartus II
Step 6: Place and route the design in the vendors tool.
Step 7. Generate the programming file in the vendors tool.
Step 8: connect the vendor's programming cable to your PC and the board, and use the vendor's programming tool to download the programming file to the device.
Step 9: Watch as your FPGA catches fire and halts. ;-) (this is a joke)

VHDL isn't used to automate FPGA routing...It's a language designed to describe a hardware design at a higher level of abstraction than hooking up gates and flip-flops in a schematic.

Thank you,
can you elaborate step_6 through step-8(I am not familiar with them but I want to know)

Verilog or VHDL language has own limitation , not all the syntax in HDLs are synthesizable.

when there was no system verilog, people used verilog or vhdl as verification language, and there you need syntax to make your simulation more effective. It is used in modelling also and there you might have to model 'X' or 'Z' , etc .. totally depend of the behavior of circuit.

hope this clear some of doubts.

Rahul

Y.SAI SARASWATHI said:

Thank you,
can you elaborate step_6 through step-8(I am not familiar with them but I want to know)

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Usually its just a case of pressing compile and checking the report outputs. If it fits and meets your timing specs, it "should" work on the target device.

It means tht if i directly write one sample all vhdl code and follow that procedure can i use it as an ic which serves particular purpose.

You post is very vague, and seems rather meaningless. yes, you write VHDL, compile it, write it to your FPGA and your circuit does hopefully what you want it to.