Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Design Compiler (Synopsys) -> Interview Questions

Status
Not open for further replies.

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
883
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,868
Hi All,

What questions might be asked in the interview for Synopsys Design Compiler Engineer (specially questions related to the flows)?

Thank you!
 

1. Difference between target/link libraries.
2.How to solve timing issues?
3.What are the different kinds of cells used?
4.Characteristics of H & LVT cells.
 

How to solve timing issues?
Applying timing constraints, flat the design, logic cloning, rebalance registers/flops, usage of LVT & HVT libs...
What are other methods?
----------------------------------------------------------------------
What are the different kinds of cells used?
Are you about LVT/HVT cells?
----------------------------------------------------------------------
4. Characteristics of H & LVT cells
What are characteristics do they have?

Thank you!
 

For the 1st q above: 2 more methods are there:ask the tool to put higher effort and cell sizing.
2nd q: Yes
3rd q:power,leakage current,fast vs slow...
 
  • Like
Reactions: ivlsi

    ivlsi

    Points: 2
    Helpful Answer Positive Rating
ask the tool to put higher effort and cell sizing
Can DC-T decide on the cells size?
What commands should be used?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top