Testing of Time interleaved ADC

I am designing a time interleaved at 800MHz. The interleaving factor is 4. Therefore each sub-ADC should work at 200 MHz.
Input frequency is 200MHz. Now the question is to find SNDR of the sub-ADC at 200MHz.
The problem is if I apply this frequency i would get a dc output. So, I chose a frequency near to the 200MHz such as 199.912MHz (using coherent sampling). Then I got SNDR.
Is this the correct way?

Thanks in advance

Hi,

Because nyquist, you should use signal frequencies lower than half of the sampling frequency.
To calculate the overall SNDR you need a frequency lower than 400MHz and take the readings of all four ADCs into account.
To calculate the SNDRof a single ADC you need a signal frequency of less than 100MHz.

Keep in mind, that if you use 199.912 MHz with a single ADC you will see a (alias) frequency of 88kHz. This also means to take an integer multiple of 2273 samples into account for SNDR analysis.

Another problem is to generate an _undistorted_ sine with 199.912 MHz .

I reccomend to use a relatively low signal frequency (maybe 1kHz) that is generated from the same clock source as the sampling frequency. With that you get reliable SNDR values. It avoids to get worse SNDR caused by phase jitter of sampling clock, phase jitter of signal frequency, alias frequencies.....

By the way... the "D" in SNDR means distortion. Every distortion of a sine signal causes overtones. Overtones are multiple of your signal frequency. Mainly x3, x5, x7 of your signal frequency. With 200MHz of signal it means 600MHz, 1000MHz ...
Afaik with your desired signal it is not possible to calculate a true SNDR.

Working with 1kHz and doing fourier analysis of your digital data you are able to seperate * signal amplitude, * distortion and * noise.

Hope this helps.
Klaus