my MUX makes glitches

I'm making a mux using 2 transmission gates, I had glitches at the output so I inserted two dummy NMOS as shown,
yet I still have these glitches
can anyone guide me how to avoi
these really affect my system as the glitches get larger in the next mux stage

Those "dummy NMOS" are only capacitors and can only
attenuate the switching charge. If you played with the
switch devices W and L you might find a place where the
Cgd*dV charges cancel and this would be better. You
could add "dummy" devices that are switched, to help
as well. This is not uncommon in circuits like sample/hold.

The glitches, though, may not be a real problem if you
position any downstream sampling strobes properly (at
end of settling time, before next mux address change).

The higher-impedance the mux input and output are,
the worse the excursion and settling time will be. You
may want to not cascade muxes and make a series of
high impedance nodes in the lineup, to store error. But
of course any shunt resistance degrades DC accuracy.

Any gate overdrive beyond what's needed to get min
leakage or min Ron, only imparts additional glitch energy
to no reward. A "smart" gate drive which pivots the switch
FET closer to the signal value can cut down switching
charge and turnoff pedestal voltage. But this comes at
a cost in terms of complexity and standby current (no
more bang-bang, rail-rail CMOS - now analog rail control
regulators, individual per channel, with all the downsides
of that baggage).

You should determine the smallest you can make the
switch devices and still meet whatever on resistance
number you are tasked with - and be sure that tasking
is valid. People make up nice round on resistance
numbers sometimes, rather than go through the error
budget and make the best all-aspects tradeoff. If
your far side of mux is just capacitive, Ron only impacts
settling time / BW. Aiming for an unnecessarily low Ron
drives you to oversize the switches and there's your
excess switching charge, tossed to the output.