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why axi bus's WREADY have 2 cycle?

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u24c02

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Hi

I'm trying to experiment axi bus.
When i set like this, WREADY is always having 2 cycle.
I dont understand why this having 2 cycle?

As i think, this should be have 1 cycle.

AWLEN 0
AWSIZE 0
AWBURST 0

Am i wrong?
 

WREADY is for data write channel, and what you listed is for address write channel. These channels are separated, and very(if not completely) independent.
Also, from what you put here, it seems you are playing with an AXI master. In this case, WREADY is the input to the AXI master, and you(as a "WREADY" receiver) have no control of it.

Try study the AMBA spec, and you'll understand more of it.
 

Hmm..
My question is why not how.
Also i already knew, wready signal is comeing from slave and not controlable.

My question is why this signal having 2 cycle?
Does make it sense?
 

What I meant is that the slave can keep wready for whatever number of cycles as it wishes. WREADY and WVALID together is used to validate the sampling of the data on AXI bus. It is not very meaningful to study a signal WREADY signal without context of other handshake signals.
It'll be great if you could update a waveform, since the information and the question is not very clear so far.
 

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