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Problems with getting FFT results of post simulation on ADC

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Post simulation on ADC

When I was designing a 60MHz 10bit Pipelined ADC, I found it tough to do a post layout simulation. The key difficulty is to get accurate FFT result.
For SRAM, ROM or Flash post simulation, I was only care about the timing delay with tolerable error up to 10%, using StarSim or UltraSIM. However, for pipelined ADC with SC structure, if accuracy similar to Spectre is needed, the simulation time is not acceptable. Does anyone have the experience in such simulation of similar design?
Thanks.
 

Re: Post simulation on ADC

codec said:
When I was designing a 60MHz 10bit Pipelined ADC, I found it tough to do a post layout simulation. The key difficulty is to get accurate FFT result.
For SRAM, ROM or Flash post simulation, I was only care about the timing delay with tolerable error up to 10%, using StarSim or UltraSIM. However, for pipelined ADC with SC structure, if accuracy similar to Spectre is needed, the simulation time is not acceptable. Does anyone have the experience in such simulation of similar design?
Thanks.
Click to expand...

Use the step response and compare it with high level models (averilog or matlab).

Some friends told me that nassda has good tools, but i don't trust.

Thanks
 

Re: Post simulation on ADC

Thanks, eda4you
--Use the step response and compare it with high level models (averilog or matlab).
Actually, I am intend to confirm whether parasitic RC would impair SNDR. I cannot understand how to quarantee performance by using step repsonse ?
 

Post simulation on ADC

I think that it is almost impossible to include the extracted parasitics to your simulation of the whole ADC in Spectre because of long simulation time. What can be done is including parasitics in the simulation of ADC blocks, then using this information in the behavioral model of ADC to estimate its effect on SNDR. Also when doing a system-level ADC design stage allow a reasonable margin in SNDR which will cover parasitics, mismatch and process variation.

About NanoSim etc: I have never used any fastspice simulator, so I do not know about their capabilities..
 

Post simulation on ADC

I think your PDK is not complete,isn't it?
 

Post simulation on ADC

our ADC is also do the post simulate,but I don't know how to do it?
 

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