sun_ray
Advanced Member level 3
The following rtl with always block synthesizes to a D-Flip flop
always @ (posedge clk or nededge rst)
if (rst)
q<= 1'b0;
else
q <= d;
The @ symbol mean whenever the event matches, statements following @ will be executed. Why will the following rtl without the always block not synthesize to a D flipflop then? What will the following rtl then synthesize to?
@ (posedge clk or negedge rst)
if (rst)
q<= 1'b0;
else
q<=d;
always @ (posedge clk or nededge rst)
if (rst)
q<= 1'b0;
else
q <= d;
The @ symbol mean whenever the event matches, statements following @ will be executed. Why will the following rtl without the always block not synthesize to a D flipflop then? What will the following rtl then synthesize to?
@ (posedge clk or negedge rst)
if (rst)
q<= 1'b0;
else
q<=d;