kaiserschmarren87
Member level 4
Hello,
I am using Virtex-4 RocketIO MGT with 12 RX channels. It works at 6.4 GS/s.
I am using MatLab to see the output of these different channels.
At present the channels sometimes get synchronized after several reset or re-programming FPGA or several read from RS232 port. ADC is the input.
I have redesigned the GT11_INIT_RX 'fsm' generated by the RocketIO Wizard. The rocketio_wrapper is designed for 6.4GS/s.
The design works for 3.2GS/s but again after several reset or re-programming FPGA.
What could be the root cause for channels not getting synchronized ?
Is it the issue with the PLL or DRP (Dynamic Reconfiguration Port) ?
Should I try debugging with ChipScope ? (My project expectation is to read the synchronous data in 12 channels at one read). Thank you.
I am using Virtex-4 RocketIO MGT with 12 RX channels. It works at 6.4 GS/s.
I am using MatLab to see the output of these different channels.
At present the channels sometimes get synchronized after several reset or re-programming FPGA or several read from RS232 port. ADC is the input.
I have redesigned the GT11_INIT_RX 'fsm' generated by the RocketIO Wizard. The rocketio_wrapper is designed for 6.4GS/s.
The design works for 3.2GS/s but again after several reset or re-programming FPGA.
What could be the root cause for channels not getting synchronized ?
Is it the issue with the PLL or DRP (Dynamic Reconfiguration Port) ?
Should I try debugging with ChipScope ? (My project expectation is to read the synchronous data in 12 channels at one read). Thank you.
Last edited: