Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Is there anybody know what is Cgs_M?

Status
Not open for further replies.
A

Alex Liao

Member level 4
Joined
Apr 8, 2013
Messages
75
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,991
It is Parasitic capacitances of the metal routing to source & drain.

What does this mean? The cap between metal and source/ drain?

Does it contribute to Cgs.(gate to source capacitance)?
 

Depending on modeling philosophy (and particularly
important to things like RF switches and CMOS PA
antenna-matching) the metallization - gate poly
fringing capacitance may be separately, specially
treated (de-lumped from the gate-source, gate-
drain silicon-thinOx-gatePoly plate and fringe) in
the layout parasitic extraction and the SPICE /
Spectre model. This has to be kind of high-level-
architected to ensure that metal parasitics are not
"double billed" (whatever is within the device extent
as-recognized, vs what is outside, needs to be kept
consistent between modeling and post-extraction).
 
Hi dick_freebird,

So based on you explanation is Cgs_M being considered in the modeling part or in the extraction part if it reflects parasitic capacitance between the gate-poly and source/ drain? To avoid being "double billed", it only has to be presented in one place.

Alex
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top