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clock distribution- calculating delays

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nats_

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Hi,
i have two questions on this topic:

1. how do i calculate a delay of certain component, if all i know is its' input capacitance?
(i have no knowledge of any resistance or even the lines' impedance).

2. given a circuit with a DLL component (like in the image), how do i calculate the insertion delay?
Capture.PNG
thanks!
 

If you are talking about simple gates or simple path below might be helpful to you.

Delay has two components = Effort delay + Parasitic delay
D= F+P
where,
F= g*h ('g' is logical effort,'h' is Electrical Effort)

g = Capacitance of diffusion/ Capacitance of reference inverter
h = Capacitance of output/ Capacitance of input

P = Diffusion cap at output/ Diffusion cap of the reference inverter (Parasitic delay of a gate is the delay when gate drives at zero load).

Look at few examples in the picture.

Feel free to correct me if i am wrong.

FYI - These pictures are not owned by me. It is used just as a reference.
 

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  • Logical-effort.jpg
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  • Parasitic-delay.jpg
    Parasitic-delay.jpg
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