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Can anyone help with a 16 bit latch in VHDL....

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manny

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latch 16 bits vhdl

Hello all,
I want to inplement a 16 bit latch in vhdl with a single reset... I like it to work the same as a RS-Latch, on power up the Q's are set to zero as the inputs go high this is latched across to the respective Q, but if the input that was latched changes back to a zero this will not change the Q that was set. And the single reset line will set all the Q's back to zero.

I can make it with lots of RS latches in schmatic but its not realy the way to go and i'd learn more with the VHDL code.

also would i be right in thinking this is were the INOUT and BUFFER commands if thats the right term would be used as im new the VHDL and still learning the basics....

hope someone can help and thank you...

Manny...
 

Here is the VHDL code for what you are looking for...

Code: 
library ieee;
use ieee.std_logic_1164.all;

entity latch_16 is
  
  port (
    din   : in std_logic_vector(15 downto 0);
    reset : in std_logic;
    dout  : out std_logic_vector(15 downto 0);
    en    : in std_logic);

end latch_16;

architecture Behavioral_latch of latch_16 is

begin  -- Behavioral_latch
process (din, reset, en)
begin  -- process
  if (reset = '1') then
    dout <= (others => '0');
  elsif (en = '1') then
    dout <= din;
  end if;
end process;
  

end Behavioral_latch;
 

Wow what can I say that was so quick.... thankyou thankyou thankyou very much for this i will study and learn from this to thanks again

all the best

Manny :)))
 

hi nand_gate thanks for the code I have tried it found that it Din switches to across to Dout but does not latch, when Din changes the Dout changes back

how would one make Dout stay high even if the Din had changed back to zero...

manny
 

manny said:
how would one make Dout stay high even if the Din had changed back to zero...

manny
Click to expand...

Hi manny,
u can drive the "en" signal to 0, and then check the dout-din transition.
Dout will remain in it's previous state, even when ur input din is changing.
The code given by the nand_gates is the correct logic for the latch.
 

Thank you for your advice Renjith, But i think im might of not made myself clear as to what im looking for and the application it will be in...

The project is to make a checking system for a rivet table that can have between 2 and 16 rivets heads on it the operator puts the rivets into each of the rivet heads then places the product to be riveted on the top of the heads, and then presses a start button the system which will be indipendent from my project will then rivet the product and the operator stats again...

as you can prob make out this is piece work and my unit check that the operator puts all ok the rivet into the heads and not just some to save time so you could say it a quality control system...

the sensing is done with inductive sensor picking up the mandrils (the wastage from the rivet) comming down a tube, at any speed and the output from the sensor will just give me a pulse and not stay on.

so the latch im looking for i can make in schmatic using 16 RS-Latches with the resets all connected together and just using the Q or Qbar as the output, and the Set as the input. The pulse from the sensor will then trip the latch and give me a output that will stay high even thou the input has gone back to zero.

All the outputs will go to a a or gate as well as a comaritor the or gate picks up any of the latch outputs and starts off a timer say 4 seconds and its at the end of this time i will check the comparitor output for the = line and the reset of the system does the rest.

like i said i can make it using 16 RS-latches in schmatic but i dont think its the way to go and i'd like to see it done in VHDL this way i can learn from it and be more better.

thank you all again for you inputs

Manny
 

Can you post the schimatics I will write the VHDL code as per that!
 

Thankyou nand_gates for your help the sch is below as you can see its simple on the schmatic for me but not in VHDL... If you could add a CE (chip enable) on it that would be helpful but only to select or de-select the chip, not as part of the latching function... thankyou very much for your help with this it is very kind of you...

Manny :)
 

Here is the code for ur circuit...
Code: 
library IEEE;
use IEEE.std_logic_1164.all;

entity sr_latch is
  port (
    s : in  std_logic;
    r : in  std_logic;
    q : out std_logic);
end sr_latch;

architecture behave of sr_latch is
signal q_int : std_logic;
signal q_bar : std_logic;
begin  -- behave
  q <= q_int;
  q_int <= s nand q_bar;
  q_bar <= r nand q_int;
end behave;

library IEEE;
use IEEE.std_logic_1164.all;
use work.all;
entity latch_16 is
  
  port (
    reset : in  std_logic;
    q     : out std_logic_vector(15 downto 0);
    din   : in  std_logic_vector(15 downto 0));
end latch_16;

architecture Behavioral of latch_16 is
component sr_latch
    port (
    s : in  std_logic;
    r : in  std_logic;
    q : out std_logic);
end component;

begin  -- Behavioral
  g1: for i in 0 to 15 generate
    comp: sr_latch
      port map(s => din(i),
               r => reset,
               q => q(i));
  end generate g1;
  
end Behavioral;
 

Thank you again nand_gates for you help... i can see what you have done. Ican learn a lot from this

thank you very much for you help...

Manny :)
 

nand_gates said:
Here is the code for ur circuit...
Click to expand...

Hello nand_gates,

It looks like you are a professional in VHDL. Could you recommend some very good books about this topic?


Thank you in advance,
cube007
 

@RDEC

Wtf... are dou doing here
Why did you upload timing specs from Microchip PIC

Admins : Would you please remove the post
and take appropriate action here :-(

/Bingo
 

thanks.. i try to use in my design..
 

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