Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Verilog synthesizable construct for a signal which changes

Status
Not open for further replies.
S

sun_ray

Advanced Member level 3
Joined
Oct 3, 2011
Messages
772
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,298
Activity points
6,828
I have a signal with 10 bit width. I want to assign do an operation while this 10 bit signal changes. Can anybody please let me know the synthesizable construct to indicate that whenver this signal 9:0 width changes , an operation can be done?

Let the signal name be is high_volt[9:0]. Whenever high_volt changes I need to do an addition of two other signals named low_volt and medium_volt.

Will @high_volt work? If you please write the complete construct to add low_volt and medium_volt.
 

The only synthesizable way is synchronous logic comparing a previous registered with the actual input value.

Level sensitive events like @high_volt work are only relevant for simulation and ignored in synthesis.
 

FvM said:
The only synthesizable way is synchronous logic comparing a previous registered with the actual input value.

Level sensitive events like @high_volt work are only relevant for simulation and ignored in synthesis.
Click to expand...

Can you please provide the complete construct in verilog of using @high_volt even if it only works for simulation. Will it need an always block? Can you please write the code portion for it in verilog?

Regards
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top