JK666
Newbie level 1
VHDL
Hi,
I have a VHDL question.Who can help me resolve this question?
I will appreciate you.Thank you.
For the following VHDL source code, with regards to the “when others” clause within the case statement, answer the following:
1a. For simulation of this model, is the “au_ result <= a + b” operation the best strategy? Explain?
1b. For synthesis of this model, is the “au_ result <= a + b” operation the best strategy? Explain?
library ieee;
use ieee. std_ logic_ 1164.all;
use ieee. numeric_ std. all;
entity au32 is
port (
a : in unsigned (31 downto 0); -- Operand A
b : in unsigned (31 downto 0); -- Operand B
opcode : in unsigned (1 downto 0); -- Opcode
au_ result : out unsigned (31 downto 0) -- arithmetic unit result
);
end entity au32;
architecture rtl of au32 is
begin
au32_ proc:
process( a, b, opcode) is
begin
case opcode is
when "00" => au_ result <= a + b;
when "01" => au_ result <= a - b;
when "10" => au_ result <= a + 1;
when "11" => au_ result <= b + 1;
when others => au_ result <= a + b;
end case;
end process;
end architecture;
Hi,
I have a VHDL question.Who can help me resolve this question?
I will appreciate you.Thank you.
For the following VHDL source code, with regards to the “when others” clause within the case statement, answer the following:
1a. For simulation of this model, is the “au_ result <= a + b” operation the best strategy? Explain?
1b. For synthesis of this model, is the “au_ result <= a + b” operation the best strategy? Explain?
library ieee;
use ieee. std_ logic_ 1164.all;
use ieee. numeric_ std. all;
entity au32 is
port (
a : in unsigned (31 downto 0); -- Operand A
b : in unsigned (31 downto 0); -- Operand B
opcode : in unsigned (1 downto 0); -- Opcode
au_ result : out unsigned (31 downto 0) -- arithmetic unit result
);
end entity au32;
architecture rtl of au32 is
begin
au32_ proc:
process( a, b, opcode) is
begin
case opcode is
when "00" => au_ result <= a + b;
when "01" => au_ result <= a - b;
when "10" => au_ result <= a + 1;
when "11" => au_ result <= b + 1;
when others => au_ result <= a + b;
end case;
end process;
end architecture;