3wais
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I'm using synopsys DC to synthesize a design, the compilation finishes with no errors, also all warnings are reasonable (unconnected signals and so).
the problem is when I check the verilog netlist I find GTECH cells! most cells are mapped to library cells as normal, but there are some unmapped GTECH cells (basic AND2/XOR2/INV cells) and some **SEQGEN** cells (I don't know what are these). why does this happen? at first I though my library was missing some cells which would cause this problem, but then in the netlist I found some mapped cells with same function. how to solve this problem? how to force DC to map these cells to library cells?
the problem is when I check the verilog netlist I find GTECH cells! most cells are mapped to library cells as normal, but there are some unmapped GTECH cells (basic AND2/XOR2/INV cells) and some **SEQGEN** cells (I don't know what are these). why does this happen? at first I though my library was missing some cells which would cause this problem, but then in the netlist I found some mapped cells with same function. how to solve this problem? how to force DC to map these cells to library cells?