Sec pole of folded cascoded opamp

Specs;
DC gain 60dB
UGB 50MHz
PM >60
VCC 2.5V

I am working on this design and DC gain & UGB is already fulfilled the spec,but the PM is always around 30 deg.
Because the sec pole is right at 63MHz and cannot be moved right(high freq).
I know the sec pole coming from the folding point, but no matter I increase the current in the cascoded branch or increase the gm of input pair, after adjusting the parameters to get enough gain, the pole will still be there. So I wonder are there anyway to change the sec pole position? Some one told me to change the biasing voltage but in the following design I need to do rail to rail amp which has one NMOS and one PMOS input pair at the same time. So I have to set the bias around the midpoint of VCC, right?

Ray.

If I good remember second pole is bounded with gm and cgs of cascode transistor.

Check this paper: **broken link removed**

Dominik Przyborowski said:

If I good remember second pole is bounded with gm and cgs of cascode transistor.

Check this paper: **broken link removed**

Click to expand...

yes, that is right. But to maintain the gain, there is only small range of trade _off but that is meanless.
Because no matter I reduce the size of that cascode MOSfet the gm will fall down or increase the size the para cap will go up.If I increase the current the Gain will be reduced by the decreasing Rout.

So try the feedforward compensation.