Design doesn't work normally in new Modelsim version

Dear all,

I've been working with Modelsim SE6.6 for years and all my simulation designs work fine. But today when I immigrate to Modelsim SE 10.1c, they don't.

For example, a process like this:

always @(posedge clk or negedge reset_n)
if(!reset_n)
message_type = 0;
else
if(cnt_reg == Packet_length)
message_type = `head;
else if((cnt_reg < Packet_length) && (cnt_reg > 1))
message_type = `body;
else if(cnt_reg == 1)
message_type = `tail;

Assume Packet_length is 4, the message type is supposed to be `head, `body, and `tail when cnt_reg is 4, 3 or 2, and 1, respectively. But in Modelsim 10.1c, it turns out to be `body, `body, `tail, 'tail, when cnt_reg is 4,3,2,1, respectively.

I assume this is related with some settings in the Modelsim.

Has anybody come accross the same problem? How you solved it?

Thanks!

Best Regards,

Changlin Chen

Problem solved.

It seems that Modelsim has some problem to recognize "cnt_reg == xxx". I have to replace this expression with a wire, e.g., head_wire, and "assign head_wire = cnt_reg == xxx" outside of the "always" process.

Why this would happen? Modelsim did too much optimization? or this is a bug in it?

Changlin