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What are the differences between SS, TT, FF corners?

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ccw27

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SS, TT, FF corner

Can anyone explain what are the main differences between the three corners (SS,TT and FF) and why the worst case is SS with 0.9Vdd @ 130°C and best case is FF with 1.1 Vdd @ -30°C.

Thanks
 

Re: SS, TT, FF corner

Best case means higher speed. Delay of CMOS gates became smaller speed higher. The same behavior of CMOS gates can cause:

Higher VCC
Lower temperature
Lower threshold voltages of NMOS and PMOS transistors.

So that's why the best case is HIGH VCC, LOW TEMPERATURE and LOW PMOS/NMOS threshold voltage (FF). And worst case is just vice versa.
 
Re: SS, TT, FF corner

the electronic's speed
 

Re: SS, TT, FF corner

Corners are usualy calculated as +/- 3 sigma values of Typical. What you indicate are simulation conditions not the SS/TT/FF spice model corners.
 
Re: SS, TT, FF corner

SS: NMOS slow, PMOS slow
FF: NMOS fast, PMOS fast
TT: NMOS typical, PMOS typical
 

Re: SS, TT, FF corner

This is not always ture. Sometimes the worst case happens at fast NMOS, slow PMOS, and so on.

ccw27 said:
Can anyone explain what are the main differences between the three corners (SS,TT and FF) and why the worst case is SS with 0.9Vdd @ 130°C and best case is FF with 1.1 Vdd @ -30°C.

Thanks
Click to expand...
 

Re: SS, TT, FF corner

Process corner simulation:
Generally,ff is the worst corner for ADC and VCO.
ss becomes worst in some cases such as logic circuits.
 

Re: SS, TT, FF corner

variation in channel length
 

Re: SS, TT, FF corner

Teddy said:
Corners are usualy calculated as +/- 3 sigma values of Typical. What you indicate are simulation conditions not the SS/TT/FF spice model corners.
Click to expand...

Actually, many fabs use +/-4sigmas AT LEAST, in their min/max parameters.
 

Re: SS, TT, FF corner

lakeoffire said:
This is not always ture. Sometimes the worst case happens at fast NMOS, slow PMOS, and so on.

ccw27 said:
Can anyone explain what are the main differences between the three corners (SS,TT and FF) and why the worst case is SS with 0.9Vdd @ 130°C and best case is FF with 1.1 Vdd @ -30°C.

Thanks
Click to expand...
Click to expand...

You probably should do all these corner simulations first and only after that you can decide which is the worst case for your particular application. Could be any parameter from power consumption, low speed, gain etc.
 

Re: SS, TT, FF corner

cretu said:
lakeoffire said:
This is not always ture. Sometimes the worst case happens at fast NMOS, slow PMOS, and so on.

ccw27 said:
Can anyone explain what are the main differences between the three corners (SS,TT and FF) and why the worst case is SS with 0.9Vdd @ 130°C and best case is FF with 1.1 Vdd @ -30°C.

Thanks
Click to expand...
Click to expand...

You probably should do all these corner simulations first and only after that you can decide which is the worst case for your particular application. Could be any parameter from power consumption, low speed, gain etc.
Click to expand...

If you consider all the permutations you can have - that's a lot of corners! And yes, there are a lot of other parameters to worry about. Now you know why analog design takes so long....
 

Re: SS, TT, FF corner

For resistor variation (min, typ, max), do you typically associate ss corner with max and ff with min or do you simulate with all possible permutation?

Thanks
 

Re: SS, TT, FF corner

The whole point of simulating something at SS is to see worst case delay.
But in case the circuits or design has some race condition then in that case worst case delay can also be visible by the cross-corner analysis.

Regarding sigma point can anybody explain which sigma(current, threshold voltage etc) actually we are talking about ?
 

Re: SS, TT, FF corner

The nature of semiconductor material is so.
You can refer to the semiconductor device physical.
 

Re: SS, TT, FF corner

The head room plays a part in what the worst case combinations is, although it's always at low VCC.
 

SS, TT, FF corner

hi, zmliu, could you explain why ff is the worst corner for ADC and VCO?
 

Re: SS, TT, FF corner

Worst Case corners in the foundry side is just referred to several extreme cases of the various process parameters (e.g. ff, ss of MOSFET). All ff, ss, sf, fs are called worst cast corners in the MOSFET.

However in the user and designer sense worst case corner is referred to the combinations of corners that leads to the most worst case performance situation, and depends on what performance the user is interested to, the same corner combination can be best case or worst case.

For example, ff corners in the mosfet can be the best case corner in terms of speed (e.g. GBW) specification, but also can be the worst case corners in terms of stability (e.g. phase margin) spec. Hope this help.
 

Re: SS, TT, FF corner

Most importantly, the corners of a process are designated by five parameters

1. Mobility variation due to implantation of N+ and P+
2. Vth variation
3. Resistance of the actives
4. Body coefficient
5. Oxide thickness

Other parameters like the effective Length, effective width, Cjsw caps, Cj caps also change. Hence Slow Slow, Fast Fast corners come into picture
 

Re: SS, TT, FF corner

Vamsi Mocherla said:
Most importantly, the corners of a process are designated by five parameters

1. Mobility variation due to implantation of N+ and P+
2. Vth variation
3. Resistance of the actives
4. Body coefficient
5. Oxide thickness

Other parameters like the effective Length, effective width, Cjsw caps, Cj caps also change. Hence Slow Slow, Fast Fast corners come into picture
Click to expand...

This is true. For a design one or maybe a couple of these possible combinations is actually "The" worst corner/situation. Depends on the application and it's recomended to check everything to be on the safe side(if the design ends up with a real product)
 

Re: SS, TT, FF corner

Weak nmos,Weak Pmos and high temperature worst corner in terms of speed (Vt is more ,currents are less ,drive is less ,very high temp mobility degrades ).

Fast nmos,Fast pmos and low temp is the best corner
 

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