Buriedcode
Full Member level 6
Hi, I usually end up writing loads when I ask for advice, I'll try to keep this short.
Right, I'm designing a fairly simple CPLD development board for a MACH4A CPLD. I would like to be able to have a wide selectable range of frequencies for the system clock without having a programmable PLL or thousands of jumper settings, trying to keep this a bit simple
k: here's my ideas:
>Gated crystal oscillator with 74HC inverter. - for high frequency <20MHz. - Crystal can be socketed.
>Gated RC oscillator with inverter (or schmitt trigger?) for low frequency <100kHz.
>Use a 4020/40/60 ripple counter to acheive a 2,4,8,16 etc.. clock division.
Using the above, I'm pretty sure a 1Hz - 20Mhz clock is possible, although in steps.
Has anyone designed something like this before? I could use jumpers to switch between crystal and RC oscs, and 8 more jumper settings for the division ratio, but I would really like to have the division available for both the crystal and the RC oscs. My CPLD has 2 oscillator inputs, I don't think I would need to use both at the same time, but I can choose which one to use in software. If I put the Xtal on one, and the RC on the other, I would have to use 2 divider chips. - don't really want to. I could use the other clock input for connection to an 'external' clock.
I'm open to any suggestions regarding a simple clock divider chip that can provide 2,4,8,16,32 and preferably 64 ratios using jumpers. Haven't found anything other than the (cmos/74HC)4060 so far. Of course, being a CPLD, it can easily do it internally, but I don't really want to waste half of a design trying to get the clock right.
Just to recap (if you haven't fallen asleep):
Crystal -> jumper -> divider (with selectable ratio) -> CPLD.
RC ->
Thankyou,
Buried(in)code.
Right, I'm designing a fairly simple CPLD development board for a MACH4A CPLD. I would like to be able to have a wide selectable range of frequencies for the system clock without having a programmable PLL or thousands of jumper settings, trying to keep this a bit simple
k: here's my ideas:>Gated crystal oscillator with 74HC inverter. - for high frequency <20MHz. - Crystal can be socketed.
>Gated RC oscillator with inverter (or schmitt trigger?) for low frequency <100kHz.
>Use a 4020/40/60 ripple counter to acheive a 2,4,8,16 etc.. clock division.
Using the above, I'm pretty sure a 1Hz - 20Mhz clock is possible, although in steps.
Has anyone designed something like this before? I could use jumpers to switch between crystal and RC oscs, and 8 more jumper settings for the division ratio, but I would really like to have the division available for both the crystal and the RC oscs. My CPLD has 2 oscillator inputs, I don't think I would need to use both at the same time, but I can choose which one to use in software. If I put the Xtal on one, and the RC on the other, I would have to use 2 divider chips. - don't really want to. I could use the other clock input for connection to an 'external' clock.
I'm open to any suggestions regarding a simple clock divider chip that can provide 2,4,8,16,32 and preferably 64 ratios using jumpers. Haven't found anything other than the (cmos/74HC)4060 so far. Of course, being a CPLD, it can easily do it internally, but I don't really want to waste half of a design trying to get the clock right.
Just to recap (if you haven't fallen asleep):
Crystal -> jumper -> divider (with selectable ratio) -> CPLD.
RC ->
Thankyou,
Buried(in)code.
