Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to check LDMOS in the saturation region when design a OPA?

Status
Not open for further replies.
M

mpig09

Full Member level 4
Joined
Aug 26, 2005
Messages
232
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Location
Taipei
Activity points
2,810
Hi all:

I wish a OPA for a LDO and the OPA operation voltage is
5~20V.

For high voltage, I use LDMOS to design the OPA, but I found there isn't have vdsat parameter in my pdk.

Do you have any suggestion or solution to know the LDMOS is in saturation region or not?

Thanks for your reply.
mpig
 

Check the Id vs. Vds characteristic of your LDMOS for the planned drain current Id. Normally it works in the saturation region if Vds > Vgs .
 

Hi erikl :

Thanks.

I will do it.

mpig
 

hi
i am working on si ldmos in ATLAS SILVACO ,it show a warning/error in running time that one contact on both side of junction . so plz tell me whats problem and how can we solve this problem
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top