Dummy metal fill to meet the density rules..

Automatic insertion of metal to meet the metal
density rules as specified by a foundry for a given
placed and routed IC in 28nm process is my project as of now.
And I need to know certain stuff as I have no idea..


1) Why do we prefer ASIC and
full-custom designs rather than FPGA ?
2) I need bit of Understanding on 28nm process technology ?
3) What are the design rules, semi-custom layout design flow, physical verification flow ?
4) Understanding of Calibre SVRF ?
5) and finally Implementation ?
6) And what is the problems in this(if density not met) ?
7) and relevance of this project(according to the present scenario, in what way this technology is helpful and how we are using it) ?



There are many questions to be answered, you can choose any one or all to answer ! In that case I will be very thankful. !

Esplendida said:

Automatic insertion of metal to meet the metal
density rules as specified by a foundry for a given
placed and routed IC in 28nm process is my project as of now.
And I need to know certain stuff as I have no idea..


1) Why do we prefer ASIC and
full-custom designs rather than FPGA ?
2) I need bit of Understanding on 28nm process technology ?
3) What are the design rules, semi-custom layout design flow, physical verification flow ?
4) Understanding of Calibre SVRF ?
5) and finally Implementation ?
6) And what is the problems in this(if density not met) ?
7) and relevance of this project(according to the present scenario, in what way this technology is helpful and how we are using it) ?

Click to expand...

Most of these questions have nothing to do with the preamble.

1) FPGA, you pay for what you use and what you don't.
Unless you find one that is exactly right, 95+% utilization
and no performance binds, a custom / ASIC implementation
will use less die area, perform better and cost less at the
same foundry - once you get to volume. But where that
breakeven lies, comes down to particulars (esp. the
engineering effort and how long it takes you to chase
out design bugs when you have a full fab cycle in between
every try).

2-5) Ask your foundry for a training dump.

6) Possibly nothing at all, but probably as a minimum some
CAD methodology harpie will try to peck your eyes out.
Fills ensure that, for example, the imbecile robotic
aligner can find an alignable feature on that layer within
its limited field of view, no matter what random place it
happens to land its eye on.

7) I have no idea whether your project is relevant.

Thanks for your time dick_freebird.
I have one more doubt..
I know that The fab has specific rules for fabricating IC s which have to be met by the design engineer ,one such rule is METAL DENSITY RULE
The IC(say Ic with 2million transistors) with more number of transistors has more metal compared to the other IC( say 1million transistors). But according the Design Rules provided by the FAB the Metal density must have a fixed range say 80 to 90 percent.
In order to meet the discrepancy in metal quantity we go for adding dummy metal to the layout in order to meet the Design Rules provided by the fab.

Why it has to be 80-90 percent only? And what are the problems we face if we fail to meet this density rules or not filled? (should we throw the whole setup if not met?)
Plz help , I have no idea AT ALL ! I need to know few stuff before researching it on my own. (This is the project title i've selected for my B.E final year, so plz help)