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DSP with FPGA: Verilog or VHDL ?

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I swear off starting another boring Verilog-vs-VHDL thread,
(besides I don't wanna break the forum rules)
but which is the most suitable HDL for DSP targetted to FPGA ?

Thanks
 

Well DSP requires a high level modeling usually done with MATLAB .So an ideal solution is ACCELFPGA wich is basically a MATLAB language compiler .
Otherwise .there are plenty of libraries of cores they produce VHDL most of the times and VERILOG too .So the HDL code produced by COREGENERATOR,SYSTEM GENERATOR .SYSTEMVIEW and others are well optimized and RTL simulation is not required .But for complicated not standart algorithms is better to use MATLAB and then migrate to something like ACCELFPGA or even CELOXICA
 

    Regnum

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But high-level language tools often provide unefficient RTL code, please refer to www.fpgajournal.com for the article - "Leading Languages - Is There a Future Beyond RTL"
 

I think Verilog is better, because it is like C, very common in engineer usage
 

Algorithm can be relatively converted to Verilog
 

they are similar tool that descript the arithmetic.
About the dsp the key is the arithmetic design.
 

verilog is better than VHDL since it supports lot of library linking file.MATLAB will also support verilog.use simulink...then if u still want to increase further performance u can go for systemC
 

beginner can easy study and do programming in verilog with basic C knowledge
verilog is better for doing vlsi DSP project
 

maybe VHDL is better for DSP targetted to FPGA because VHDL has abundant data types to describe the algorithm.
 

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