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8*8 verilog multiplier

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sresam89

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The attached is a code fro 8*8 mulitplier this doesnot work. tried simulating with modelsim and xilinx ISM

I want it to be a normal multiplier using addition by the integer value.

please help

Code:
 `timescale 1ns / 1ps

module multi8_8(input [7:0] x,y,input clk, output [15:0] z );

	wire [7:0] x_temp,y_temp;
	reg [15:0] z_temp;
	

/*initial
begin
assign z_temp = 16'b0;
end
*/

assign x_temp = (x[7]==1)? ~x+1:x;
assign y_temp = (y[7]==1)? ~y+1:y;

integer x_int,y_int;

always @ (x_temp)
begin
x_int=x_temp;
$display(x_int);
end

always @ (y_temp)
begin
y_int=y_temp;
$display(y_int);
end

integer i;
always @ (x_int or y_int)
begin
	if(x_temp>y_temp)
		for(i=0;i<y_int;i=i+1)
		begin	
			 z_temp=z_temp+x_temp;//[B]I THINK THIS LINE DOES NOT EXECUTES GIVES ZEROS ALWAYS[/B]
			$display(i);//this seems to display the correct iteration
			$display(z_temp);//[B]This displays always zero[/B]
		end
	else
		for(i=0;i<x_int;i=i+1)
		begin	
			z_temp=z_temp+y_temp;//[B]I THINK THIS LINE DOES NOT EXECUTES GIVES ZEROS ALWAYS[/B]
			$display(i);//this seems to display the correct iteration
			$display(z_temp);//[B]This displays always zero[/B]
		end
end
assign z=z_temp;//no result either xxxx or zeros
endmodule
 

The code doesn't describe synthesizable hardware. It looks like you don't understand what a HDL for loop means. It's a method to replicate hardware elements, not performing a sequence in time.

The code can probably run in simulation if z_temp is cleared before the loop.

Adding the multiplicator n times is also the worst way to make a multiplier, I think.
 

The code doesn't describe synthesizable hardware. It looks like you don't understand what a HDL for loop means. It's a method to replicate hardware elements, not performing a sequence in time.

The code can probably run in simulation if z_temp is cleared before the loop.

Adding the multiplicator n times is also the worst way to make a multiplier, I think.

Thank you for your comments i solved it myself in another way.
 

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