[SOLVED] Non-Blocking assignment

always@(posedge clk)
begin
	PC <= Next_PC ;
	rt_mux2 <= {{16{Instr[15]}},Instr[15:0]} ;
	ALU_op_reg <= ALU_op;
	rs_reg <= rs ;
	J1 <= Instr[25:0] ;
	J2 <= J1 ;
	PC1 <= PC ;
	PC2 <= PC1 ;
	PC3 <= PC2 ;

end

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date:    00:34:19 01/24/2014 
//////////////////////////////////////////////////////////////////////////////////
module TOP_1(
    input clk,
    input Instr_read,
    input Instr_write,
    input [31:0] instr_in
    );

reg [29:0] PC ;
///////////////////////////Instr cache////////////////////////////////
wire [31:0] Instr;   // Full Instruction 
Instrcache Instr_cache(.PC(PC),.inst(Instr),.Instr_read(Instr_read),.Instr_write(Instr_write),.instr_in(instr_in),.clk(clk) ) ;
///////////////////////////Controller////////////////////////////////
wire RegWrite ;
wire [1:0] RegDst ;
wire [1:0] RegInSrc ;
wire ALUSrc ;
wire Add_Sub ;
wire [1:0] LogicFn ;
wire [1:0] FnClass ;
wire DataRead ;
wire DataWrite ;
wire [1:0] BrType ;
wire [1:0] PCSrc ;
wire [1:0] Shift_Fn;
Controller_2 Contr(.op(Instr[31:26]),.fn(Instr[5:0]),.clk(clk),.RegWrite(RegWrite),.RegDst(RegDst),.RegInSrc(RegInSrc),.ALUSrc(ALUSrc),.Add_Sub(Add_Sub),.LogicFn(LogicFn),.FnClass(FnClass),.DataRead(DataRead),.DataWrite(DataWrite),.BrType(BrType),.PCSrc(PCSrc),.Shift_Fn(Shift_Fn) ) ;
///////////////////////////mux1 3_1_5////////////////////////////////
wire [4:0] Rd_addr ;
mux3_1_5 mux1(.A(Instr[20:16]),.B(Instr[15:11]),.C(5'd31),.sel(RegDst),.D(Rd_addr) ) ;
///////////////////////////Reg File ////////////////////////////////
wire [31:0] rs ;
wire [31:0] rt ;
wire [31:0] rd ; //this will the output of last mux
//--here rd is missing till i add the mux 3 it will be inputed
Regfile Reg_file(.rs_addr(Instr[25:21]),.rt_addr(Instr[20:16]),.rd_addr(Rd_addr),.rs(rs),.rt(rt),.rd(rd),.RegWrite(RegWrite),.clk(clk) ) ;
///////////////////////////mux 2_1////////////////////////////////
reg [31:0] rt_mux2 ;
wire [31:0] ALU_ip_2;
mux2_1 mux2(.A(rt),.B(rt_mux2),.sel(ALUSrc),.D(ALU_ip_2) ) ;
///////////////////////////ALU////////////////////////////////

//equal_less is used in case of set if less than or equal and set if less than and set if equal or not less than or not equal
wire [31:0] ALU_op;
ALU_new ALU(.A(rs),.B(ALU_ip_2),.C(ALU_op),.ovfl(),.add_sub(Add_Sub),.equal_less(1'b1),.logic_fn(LogicFn),.shift_fn(Shift_Fn),.fn_class(FnClass) ) ;
///////////////////////////Data cache////////////////////////////////
wire [31:0] cache_mux3;
Datacache Data_cache(.Data_addr(ALU_op[6:0]),.Data_out(cache_mux3),.Data_Read(DataRead),.Data_Write(DataWrite),.Data_in(rt),.clk(clk) ) ;
///////////////////////////mux2 3_1////////////////////////////////
reg [31:0] ALU_op_reg;
wire [29:0] Incr_PC;
mux3_1 mux3(.A(cache_mux3),.B(ALU_op_reg),.C(Incr_PC),.sel(RegInSrc),.D(rd)) ;
///////////////////////////Next addr////////////////////////////////
wire [29:0] Next_PC ;
reg [31:0] rs_reg;
reg [25:0] J1;
reg [25:0] J2;
reg [29:0] PC1;
reg [29:0] PC2;
reg [29:0] PC3;

Next_addr Nextaddr(.A(rs_reg),.SysCallAddr(),.PC(PC3),.J(J2),.Incr_PC(Incr_PC),.Next_PC(Next_PC),.PCsrc(PCSrc),.Br_Type(BrType) ) ;

always @ (posedge clk )
begin
	PC <= Next_PC ;
	rt_mux2 <= {{16{Instr[15]}},Instr[15:0]} ;
	ALU_op_reg <= ALU_op;
	rs_reg <= rs ;
	J1 <= Instr[25:0] ;
	J2 <= J1 ;
	PC1 <= PC ;
	PC2 <= PC1 ;
	PC3 <= PC2 ;
end
endmodule

Instrcache Instr_cache(.PC(PC),.inst(Instr),.Instr_read(Instr_read),.Instr_write(Instr_write),.instr_in(instr_in),.clk(clk) ) ;