[SOLVED] Drc versus lvs. Bulk substrate connection

I am trying to produce a clean LVS and DRC.

According to my schematic, a PFET (non-isolated) transistor has its bulk connected to VDD. Therefore in the layout I have connected the bulk of the PFET device to VDD. Furthermore the p-substrate of the PFET device is connected to ground. According to the DRC rules, the p-substrate(connected to ground) must be tied to the bulk(connected to VDD) and hence a clean DRC is obtained. But on the other hand when I run the LVS is get a ”Power supply abort error”, due to the tie connection required by the DRC rules between bulk and p-substrate, Obviously due to the supply short between VDD (bulk) and GND(p-substrate).Introducing a GRLOGIC layer around the p-sub of the PFET device produces a clean DRC and does not generate the LVS “power supply abort” error.

I this stage I got stuck and I don`t know how to proceed further, because my design requires that the bulk input to be connected to VDD and not to be tied to ground as required by the DRC.

Can someone suggest how should i proceed.

Thanks.

A PFET must sit in its own n-doped region, this is the BULK for the PFET. The BULK of the PFET should connect to VDD (n-doped region). Im not sure what you mean about the p-substrate of the PFET.

The substrate which connects the grounds is p-doped.

Maybe do a screen grab of the schematic and layout (with layers) for better help.

DharmaSlice said:

A PFET must sit in its own n-doped region, this is the BULK for the PFET. The BULK of the PFET should connect to VDD (n-doped region). Im not sure what you mean about the p-substrate of the PFET.

The substrate which connects the grounds is p-doped.

Maybe do a screen grab of the schematic and layout (with layers) for better help.

Click to expand...

Hi DharmaSlice,

Thanks for your reply.Attached are screen shots showing the DRC error, schematic and layout for the pfet device.
If the pfet device is connected with the MPP guard Ring of tempalte RX_BP_M1, then the DRC error is cleared, but then the LVS fails because source and bulk which should be connected to vdd are then shorted to ground when tied with ring as required by DRC rule checked.


https://obrazki.elektroda.pl/7856222800_1390755541.png

https://obrazki.elektroda.pl/6034589200_1390755542.png

Thanks for your help.

Regards,
Clive

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DharmaSlice said:

A PFET must sit in its own n-doped region, this is the BULK for the PFET. The BULK of the PFET should connect to VDD (n-doped region). Im not sure what you mean about the p-substrate of the PFET.

The substrate which connects the grounds is p-doped.

Maybe do a screen grab of the schematic and layout (with layers) for better help.

Click to expand...

Hi DharmaSlice,

Find attachments showing parts of schematic, layout and DRC error. If bulk is connected with MPP Ring of type RX_BP_M1 then DRC error is cleard but LVS fails because since bulk which is connected to VDD will then short with gnd of MPP ring.

Thanks.

Are there two rings in place? If so the n+ring surrounding the pfet should go to VDD. The outer ring would go to GND.

MSLayout said:

Are there two rings in place? If so the n+ring surrounding the pfet should go to VDD. The outer ring would go to GND.

Click to expand...

This sounds correct to me. @clive.seguna@gmail.com : 'If bulk is connected with MPP Ring of type RX_BP_M1' --- Im not used to this terminology, what type layer is this. It sounds like a Ground P-type connection ?

From the layout view Id connect the inner ring to VDD (only because the purple looks like NWELL to me) and the outer to VSS.

Does this help ?

DharmaSlice said:

This sounds correct to me. @clive.seguna@gmail.com : 'If bulk is connected with MPP Ring of type RX_BP_M1' --- Im not used to this terminology, what type layer is this. It sounds like a Ground P-type connection ?

From the layout view Id connect the inner ring to VDD (only because the purple looks like NWELL to me) and the outer to VSS.

Does this help ?

Click to expand...

I am new to this technology, but the RX is an N-WELL, BP is P-well, M1 is Metal. According to the design rules the bulk must be tied to an RX layer, and therefore I have added that outer ring.But then the outer ring must be tied to gnd! or sub!.At this moment the DRC is clean but whn I run the LVS it will fail as power supply abort.

THnaks.

Regards,
CLive

The BULK of a PFET is the NWELL connection, no ?

Have you connected the RX to the power supply ? and the outer ring to GND ? ---- what result did you get then.

Keep in mind just because its DRC clean doesn't make it electrically correct at all.

You could also disconnect both and re-run calibre and let it show you which connections are yet to be made.