Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Alternate clock edge detection

Status
Not open for further replies.
How about something like this?


Edge detection.png
 
Rising edge triggered D type and two and gates?

D type wired as a divide by two with the Q and *Q outputs anded with the clock to give even and odd outputs that are the same width as the clock (There might be a slight glitch due to the prop. delay of the D type).

Nick deans circuit does not match the clock timing and in any case if that is all that is required a simple D type /2 is very much easier.

Regards, Dan.
 
Dan Mills said:
Rising edge triggered D type and two and gates?

D type wired as a divide by two with the Q and *Q outputs anded with the clock to give even and odd outputs that are the same width as the clock (There might be a slight glitch due to the prop. delay of the D type).

Nick deans circuit does not match the clock timing and in any case if that is all that is required a simple D type /2 is very much easier.

Regards, Dan.
Click to expand...

Thank you Dan, Can you be specific about how circuit schematic looks like for a D/2?
 

Google "d type divide by two", it is about as simple as it gets.

Dan.
 


Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top