opamp input offset voltage...

i want to know what is opamp's input offset voltage????
what are the reasons which causes it.....


please answer me as soon as possible.....
:-|

This happens due to unbalanced doping characteristics on pair transistors at input.
Even both built at same silicon chip, it is not possible ensure the same electrical properties due to imprecise manufacturing process.


+++

Following from the above, Vt mismatch is one of the dominant causes.

This is why the input diff pair of an opamp is made large (Vt mismatch reduces by 1/sqrt(W.L)).
I suggest you read Marcel Pelgroms now famous paper on the subject, it will clear a lot up for you.

Output offsets are then typically due to assymetries in the op amp architecture. For example, in the
conventional 5 transistor OTA, the drains of the input diff pair see different impedances thereby causing
offset (Symmetrical OTAs or Folded cascodes dont have this problem).

I think, your question "what is opamp´s offset voltage" has not yet been answered.
Here is my answer: It is the dc voltage to be applied between both input nodes, which is necessary to produce a dc output voltage of zero volts.

that means this the voltage which we provide from outside to make the opamp o/p voltage 0 in absence of any i/p signal.....???

A simple measurement is to put the op amp in unity gain
feedback, ground the + input and measure the output
(which is also the - input). Badda-bing, Vio on a plate.

But Vio is often impractical to measure, bare, in a common
noisy lab environment so a more elaborate network with
an auxiliary gain amp and divider networks is more often
used for production test / characterization.

Vio has various contributors. The input pair is an obvious
one, and all you can do with that is size your way out of
mismatch until it costs you something else. But what I
see over and over is, the asymmetry at the back of the
amplifier (I don't do much fully differential stuff) divided
by the gain in front of it, becomes an input referred offset
term. So you want the circuit to have a balanced differential
form through as much of the gain chain as possible, and as
much of the gain as practical developed within the differential
portion.