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You can't. There is no such thing as "no" (zero) jitter
or skew.
If you had a meaningful, quantitative upper limit to these
then you could have a chance of meeting that goal. But
if your goal is zero, you may as well quit and go into
management before you smarten up and become useful.
Then you can have all the =0 goals you want and it's
Somebody Else's Problem.
Topology would depend on the relation / character of
the phases. A 5-stage ring oscillator would produce a
field of overlapping phases. A Johnson counter would
produce 5 nonoverlapping ones, as might a marching-
bit shift register (these, requiring a 5X clock input).
A shift register or binary counter plus poor-boy ROM
could produce you an arbitrary phase relation /
pulse width.
But nobody knows what you really want besides you
and whoever tasked you.
Hi Dick_freebird!
Thanks for your reply. I used a Johnson counter and ripple counter to generate 5 phase clocks. But, when it comes to the last flip-flop there is a long skew which is collected along the path. Is there any way I could generate with low skew? I am looking for low power consumption.
A synchronous counter will not have discrepant delays.
You could also re-register the ripple counter output by
the main clock and re-align them all (to the base delay
mismatch of whatever element you use) - an octal DFF
might be good, but not sure whether any of the octal
standard parts are FFs or just latches.
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