Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

xilinx : ram,latches

Status
Not open for further replies.
A

anoperson

Newbie level 4
Joined
Jan 3, 2014
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
43
In xilinx how can one ensure that the synthesis tool will accept an array(0 to 255) of std_logic_vector(7 downto 0) is interpreted as ram and not luts.
I may need asynchronous write operation.

Also how to avoid latch inference for internal signals? What will be problems faced if latches are used?
 

The only way to ensure you get a ram, is to follow the ram template in the coding guidelines. And for Xilinx, you must have synchronous read and write.

Avoid latch inference by either making all signals synchronous or make sure they are assigned a value in ALL cases for an async process. THe best way to to assign a default assignment at the top of a process.

Did you have any specific code in mind?
 

Just like TrickyDicky said, use the templates as stipulated in the coding guidelines aka Xilinx Libraries Guide in your case. And to verify that what you get from the synthesizer is what you intended, you can check the results with "View RTL Schematic" and "View Technology Schematic". I always find those quite useful when I am not entirely sure the synthesizer (xst) is doing what I want.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top