Bias voltages in folded-cascode amplifier

I am trying to simulate the following circuit



How do I choose Vbias1 and Vbias2? At a guess,

For Vbias1: To ensure Q5/6 are in saturation, the voltage at the drain of Q3/4 needs to be |Veff| > |Vgs|-|Vth|, thus Vbias1 > 2|Veff| + |Vth|. But then I am lost as to what the Veff will be. If I assume a 1/1/1 ratio of transistors 11/3/4 and ensure that the current in each branch is equal then they should be saturated at some value...

For Vbias2: For Q9/10 to be in saturation, Veff(9/10) > Vgs - Vth, so Vbias2 > 2Vgs + Vth but then the drain of Q7 will be at the same voltage as the gate of Q9, which to me indicates that one of those transistors can not be saturated?

Thanks for any help.

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Tied in with the above, I have calculated the different values I want to use for Ibias1 and Ibias2 according to sharing a max total current with a 4:1 ratio between the diff stage and the cascode stage currents. From those currents, if I choose a standard value for Veff I could calculate sizes for the transistors. Obviously, increasing Veff will reduce the required transistor sizes. But how would I go about picking a value?! Is there some kind of guideline anyone could give me.

I am just trying to get a circuit working so I can play with it.

Hi BartiebyScrivener

I think: Vb2 = Vtn + Vdsat7 + Vdsat9
Vb1 = VDD - (Vdsat4 + Vdsat5 + Vtp)

Choose Vdsat 7 + vdsat9 and (vdsat5 + vdsat9) small if want high output swing

Take a look at this thread. The circuit provided there with the correct sizes would automatically give the correct voltages across corners/temperatures.

https://www.edaboard.com/threads/304811/#post1305925

Refer to " Generation of gate voltage, Active Current Mirrors, Design of Analog CMOS Integrated Ckts, by Behazad Razavi".

The way bais is generated in cascode CMOS current mirrors, the same ckt can be used to bias cascode MOSFETs in the folded cascode amplifier.
The ckt look like a low voltage baising .... refer to the book and you will definitely get a deeper insight ....