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size difference between design vison and encounter

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muzammil007

muzammil007

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Hello everyone,

I am a newbie in usage of cadence tools. I used design vision to estimate the area of my design. I obtained certain area. When i used encounter after this in order to place and route, I end up getting area higher than that obtained in design vision. I really don't get what could be the reason behind it. Can anybody help?

Regards
maxx
 

There are many aspects to cause the size different, both tools are running with different optimization method, this is normal to have size different but not more than 20% different btw both.

I only can guess the constraints in both could be different, e.g in synthesis you have use WLM, (top, enclosure, segmented) but i synthesis the RC are calculated based on the interconnect wire delay. The over constraint or too optimistic constraint in synthesis will give you different optimization thus area could be different later during PnR.
 

Synopsys Design vision: performs the logic synthesis and converts the behavioral-level design into a gate-level netlist in Verilog.
Cadence Encounter: Automatic placement and routing is achieved encounter.
 

you sould compare Design Vision with Encounter RC, and with same wire-lenght model.
 

Maybe you should be care of that how the area is calculated by APR tool.
Generally speaking, the area reported by APR tool is chip area instead of cell area.
Therefore, "utilization" / "layout of macro" / "wire connection" may affect the chip area.
 

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