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If You have one fet with i.e. 100u/1u dimensions with 20Ohm/square of poly resistance You obtain 2kOhms gate resistance for one finger, 20 Ohms for 10 fingers and only 0.2 Ohm for 100 fingers.
It caused by parallel connection of gate resistance in multifinger layout.
The effective gate resistance for one-sided connected poly is Rg=1/3*W/L*rsh
where W is the gate width, L is the gate length, rsh is the sheet resistance of poly.
For two-sided connected poly, Rg=1/12*W/L*rsh.
Now, if you keep total gate width constant, and replace one finger with gate width W by N fingers each having gate width W/N - then:
1. you reduce each finger resistance by a factor of N (now Rg of one finger is Rg=1/3*W/L/N*rsh), and
2. N fingers in parallel have total effective resistance 1/Nth of each finger.
So, the total decrease of effective gate resistance is by a factor of 1/N^2.
For example, if you split one transistor finger into two fingers (keeping total W the same) - gate delay will decrease 4x.
Why, when you combine N fingers, their gate resistance decrease by a factor of N?
There are two possible explanations or interpretations:
1. when N fingers are connected in parallel, their gate resistors are connected in parallel, thus the total gate resistance is 1/Nth of gate resistance of one finger.
2. think of gate delay - tau=RC. Combining N fingers in parallel, the delay time does not change, it is still tau=RC (assuming each finger behaves independently of each other, i.e. they charge synchronously).
But, the total capacitance is N*C - so, obviously, the resistance should be R/N.
This is basic stuff.
Complications come form several different angles:
1. when you combine many fingers together - thousands or hundreds of thousands of fingers, like in power transistors (their gate width can be as large as 1-10 meters!) - resistance of metal routing of the gate network becomes significant, and may affect or even dominate the gate resistance. Gate delay and gate resistance analysis may require a use of special software tools (ask me if you want to know more about this).
2. Transistor switching - especially in power transistor, with large Vds voltage - is a strongly nonlinear process with its own delays, where device Cgs, Cgd, Cds, Vt, Vgmax, and other parameters play an important role - in gate delay, power losses, etc. There is plenty of literature on these effects, just Google it.
3. Gate resistance is a very crude parameter, it does not reflect the whole picture or the dynamics of transistor switching.
Parts of the transistor that are close to the gate port will switch faster, and parts of device far away from the gate port - slower, than the device on average.
This may be very important in large-area device switching, where switching non-uniformity may lead to dynamic current crowding, localized heating, current shoot-through (when both low-side and high-side transistors in the DC-DC converter are open at the same time).
4. Gate resistance may lead to a number of other negative effects, such as dynamic transistor opening (due to dV/dt effect on the drain and gate voltage going above Vt temporarily in areas of device with large gate resistance).
5. In sensitive analog circuits (such as low noise amplifiers - LNA), gate resistance is one of the main noise sources, which should be minimized.
6. In modern technologies (20nm and below) utilizing FINFETs, gate resistance is much more complex and more important - due to complex gate structure shapes, materials (many different materials used), complexity of simulation, etc.
7. In addition to lateral gate resistance, there may be other resistance components - such as vertical resistance, due to the interface between poly and poly silicide - and this resistance scales as 1/(W*L) - i.e., it increases at smaller transistor geometries.
Using multiple fingers in a gate reduces the amount of poly - drain area (lower resistance). Better still, connect the gate at both ends to further reduce resistance along the width of the gate.
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