Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

input offset voltage

Status
Not open for further replies.

ed_gops

Newbie level 3
Joined
Dec 8, 2013
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Location
Visakhapatnam
Activity points
34
Hi.. I found in an IEEE conference paper that the input offset voltage of a basic two stage CMOS differential amplifier as given two pics bellow. Can any one please explain me how the input offset voltage formula can be derived from the given circuit and what dose the Δ(W/L) indicate and how to calculate it. Capture.PNGCapture1.PNG. Thank you.
 

Hi ed_gops,

the delta(W/L) and delta(Vth) are random variables. Due to random physical effects during manufacturing, such as random dopant fluctuation (RDF) and line edge roughness (LER), every transistor has a slightly different Vth and L than its neighbors. This difference causes offset in a differential pair.
The formula in your picture calculates the offset for one differential pair given the values of the random variables.
The statistics of offset can be calculated from the formula: the mean value of offset is 0, the variance depends linearly on the variance of delta(W/L) and delta(Vth). These variances depend on the area of the devices by Pelgrom's area law.

Regards,
Michael
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top