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PLL not getting locked

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senmerida

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Hi,
I've designed a PLL and simulated it using Cadence Virtuoso ADL. Output of the VCO is directly given as a feedback to the reference clock pulse port of the PFD. After some time, the waves ClK1 and VCo_Out is getting locked. But it is getting off the lock after a while. How can I lock it? Requesting help.

Thanks.
 

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  • 3.Loop_out2.png
    3.Loop_out2.png
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Sounds like the loop compensation is not correct.
 

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How can i correct the loop compensation? Do i need to add another circuit or is it to do with the design?
 

Since few of us are clairvoyant, I don't see how can that question can be readily answered when you haven't posted the circuit design...
 

Hi senmerida
From my experience you should check charge pump circuit to see mismatch of up and down current. I have same problem
before. Loop filter component you can calculate easy from formular in any text book
 
Specs:
Input clk freequency 1GHz (period- 1ns)
VCO Output: 1GHz
Loop BW = 1/10 th of Input frequency = 100MHz
phase margin = 52.36

PFD : Using TSPC
w=2um, L= 180nm

Chargepump: Single ended
Current = 530uA

Loop filter : 1st order
C1 = 1.72pF
C2 = 12.811pF
R1 =10.66 KOhms

VCO Design : 5 stage current starved architecture

wp = wn = 15um (for current starved MOS)
wp = wn = 2um (for inverter stages)
L = 360nm

1.PLL_schematic.png
 

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