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Is ASIC implemented in SOI better than in bulk

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SC3K01

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Hi there,

I heard that some of CPU's are implemented in SOI process.
Is it a good approach to implement ASIC in SOI process?
 

Check IBM site, u will find many material on same.
 

Only when the off state leakage is too high to bear. SOI is best used for 90nm and below for large designs as the power dissipation in standard CMOS approaches the need for one nucear power plant per processor. Intel is beginning to realise this while AMD is already using SOI (I think).
Also if you need really low power CMOS then SOI is an option. But it is more expensive than CMOS and also, since the bulk of the transistors are isolated by Silicon Dioxide (from the substrate) heat and hot electron dissipation to the bulk can be a problem.
 

dear
SOI is good for the low power CMOS design as it overcome many critical issues like latchup,static power consumption etc.
it is better for reduced Vdd operation as they shows following properties
1. they shows reduced source and drain to substrate capacitance because of elemination of std junction of BULK MOSFET.

2.as transistors are totally isolated from each other they do not exhibit BODY effect that decreases current drive in stacked devices.also they are not subjected to CMOS LATCHUP.

3.as their body floats it couple to gate potential resulting in higher ON/OFF current ratio than BULK MOSFET.

hope it explains.
 

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