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vhdl problem with latches from incomplete statements

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ghattasak

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hello i am having a problem with the vhdl code i have tried assigning all wires to a value but couldnt solve the latche error
can anyone help me and clarfiy the problem? and how can it be solved?


WARNING:Xst:737 - Found 1-bit latch for signal <ctr_rst>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ldata>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <startsort>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

here is my statemachin:
Code VHDL - [expand]
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-----------------------------------------------------------------
   clocked_proc : PROCESS ( 
      clk,
      reset
   )
   -----------------------------------------------------------------
   BEGIN
      IF (reset = '1') THEN
         current_state <= s0;
      ELSIF (clk'EVENT AND clk = '1') THEN
         current_state <= next_state;
      END IF;
   END PROCESS clocked_proc;
 
   -----------------------------------------------------------------
   nextstate_proc : PROCESS ( 
      current_state,
      done_load,
      wr_d
   )
   -----------------------------------------------------------------
   BEGIN
      CASE current_state IS
         WHEN s0 => 
            IF (wr_d = '0') THEN 
               next_state <= s0;
            ELSIF (wr_d = '1') THEN 
               next_state <= s1;
            ELSE
               next_state <= s0;
            END IF;
         WHEN s1 => 
            IF (done_load = '0') THEN 
               next_state <= s1;
            ELSIF (done_load = '1') THEN 
               next_state <= s2;
            ELSE
               next_state <= s1;
            END IF;
         WHEN s2 => 
            next_state <= s2;
         WHEN OTHERS =>
            next_state <= s0;
      END CASE;
   END PROCESS nextstate_proc;
 
   -----------------------------------------------------------------
   output_proc : PROCESS ( 
      current_state,
      done_load,
      wr_d, startsort,ldata,ctr_rst
   )
   -----------------------------------------------------------------
   BEGIN
 
      -- Combined Actions
      CASE current_state IS
         WHEN s0 => 
            ldata <= '0' ;
                sver_en <='1';
                startsort <='0';
                ctr_rst <= '0';
            IF (wr_d = '0') THEN 
               sver_en <= '1' ;
               startsort <= '0' ;
                    ldata <= '0';
                    ctr_rst <='0';
            ELSIF (wr_d = '1') THEN 
               ldata<= '1';
                    sver_en <= '1' ;
               startsort <= '0' ;
                    ctr_rst <='0';
            END IF;
         WHEN s1 => 
                    ldata <= '1';
                    sver_en <= '1' ;
               startsort <= '0' ;
                    ctr_rst <='0';
            IF (done_load = '0') THEN 
               sver_en<= '1' ;
               startsort <= '0' ;
                    ldata <= '1';
                    ctr_rst <='0';
            ELSIF (done_load = '1') THEN 
               ldata <= '0' ;
                    ctr_rst <= '1';
                    sver_en <= '1' ;
               startsort <= '0' ;
            END IF;
         WHEN s2 => 
            startsort<= '1';
            sver_en<= '1';
            ldata <= '0';
     ctr_rst <= '0';
 
         WHEN OTHERS =>
            NULL;
      END CASE;
   END PROCESS output_proc;
 
Last edited by a moderator:

ghattasak said:
hello i am having a problem with the vhdl code i have tried assigning all wires to a value but couldnt solve the latche error
can anyone help me and clarfiy the problem? and how can it be solved?


WARNING:Xst:737 - Found 1-bit latch for signal <ctr_rst>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <ldata>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <startsort>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

here is my statemachin:
Code VHDL - [expand]
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-----------------------------------------------------------------
   clocked_proc : PROCESS ( 
      clk,
      reset
   )
   -----------------------------------------------------------------
   BEGIN
      IF (reset = '1') THEN
         current_state <= s0;
      ELSIF (clk'EVENT AND clk = '1') THEN
         current_state <= next_state;
      END IF;
   END PROCESS clocked_proc;
 
   -----------------------------------------------------------------
   nextstate_proc : PROCESS ( 
      current_state,
      done_load,
      wr_d
   )
   -----------------------------------------------------------------
   BEGIN
      CASE current_state IS
         WHEN s0 => 
            IF (wr_d = '0') THEN 
               next_state <= s0;
            ELSIF (wr_d = '1') THEN 
               next_state <= s1;
            ELSE
               next_state <= s0;
            END IF;
         WHEN s1 => 
            IF (done_load = '0') THEN 
               next_state <= s1;
            ELSIF (done_load = '1') THEN 
               next_state <= s2;
            ELSE
               next_state <= s1;
            END IF;
         WHEN s2 => 
            next_state <= s2;
         WHEN OTHERS =>
            next_state <= s0;
      END CASE;
   END PROCESS nextstate_proc;
 
   -----------------------------------------------------------------
   output_proc : PROCESS ( 
      current_state,
      done_load,
      wr_d, startsort,ldata,ctr_rst
   )
   -----------------------------------------------------------------
   BEGIN
 
      -- Combined Actions
      CASE current_state IS
         WHEN s0 => 
            ldata <= '0' ;
                sver_en <='1';
                startsort <='0';
                ctr_rst <= '0';
            IF (wr_d = '0') THEN 
               sver_en <= '1' ;
               startsort <= '0' ;
                    ldata <= '0';
                    ctr_rst <='0';
            ELSIF (wr_d = '1') THEN 
               ldata<= '1';
                    sver_en <= '1' ;
               startsort <= '0' ;
                    ctr_rst <='0';
            END IF;
         WHEN s1 => 
                    ldata <= '1';
                    sver_en <= '1' ;
               startsort <= '0' ;
                    ctr_rst <='0';
            IF (done_load = '0') THEN 
               sver_en<= '1' ;
               startsort <= '0' ;
                    ldata <= '1';
                    ctr_rst <='0';
            ELSIF (done_load = '1') THEN 
               ldata <= '0' ;
                    ctr_rst <= '1';
                    sver_en <= '1' ;
               startsort <= '0' ;
            END IF;
         WHEN s2 => 
            startsort<= '1';
            sver_en<= '1';
            ldata <= '0';
     ctr_rst <= '0';
 
         WHEN OTHERS =>
            NULL;
      END CASE;
   END PROCESS output_proc;
Click to expand...

i guess the last

WHEN OTHERS =>
NULL;

is what create the latches...
 

If you have a default value, assign it at the beginning of the process. Then you can be sure that no latch will be created.
This will also often make it possible to simplify the code:

Code VHDL - [expand]
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output_proc : PROCESS ( 
      current_state,
      done_load,
      wr_d, startsort,ldata,ctr_rst
   )
   -----------------------------------------------------------------
   BEGIN
 
      -- Default assignments 
      ctr_rst <= '0';
      ldata <= '0' ;
      startsort <='0';
 
      -- Combined Actions
      CASE current_state IS
         WHEN s0 => 
            sver_en <='1';
            IF (wr_d = '0') THEN 
               sver_en <= '1' ;
            ELSIF (wr_d = '1') THEN 
               ldata<= '1';
               sver_en <= '1' ;
            END IF;
         WHEN s1 => 
            ldata <= '1';
            sver_en <= '1' ;
            IF (done_load = '0') THEN 
               sver_en<= '1' ;
               ldata <= '1';
            ELSIF (done_load = '1') THEN 
               ctr_rst <= '1';
               sver_en <= '1' ;
            END IF;
         WHEN s2 => 
            startsort<= '1';
            sver_en<= '1';
 
      END CASE;
   END PROCESS output_proc;


Now it is easy to see that you have a problem with the "sver_en" signal, you only assign '1' to it.

I recommend you to write the state machine as one clocked process. That will eliminate all latches and make life simpler.
I don't understand why textbooks very often us the two-process style. Can it be a heritage from long ago when registers were expensive? Today registers are cheap, and the one-process style is normally better.

Also, the two-process style implies logic after registers, and that doesn't map well to current FPGA's. The single process style maps much better to FPGA's, and the outputs will be glitch-free.
 

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