how to scale down inductor and capacitor values for changing from one tech to another

hai,
i am designing VCO circuit using 45nm tech
i found VCO topology in one paper with W/L ratio of FETS and inductor value (2.4nH) for 180nm tech given in that paper
mosfet W/L ratio is cal by keeping L as 45nm
my question is how to scale inductor value for 45 nm tech
thanks in advance

venkateshjuturu said:

hai,
i am designing VCO circuit using 45nm tech
i found VCO topology in one paper with W/L ratio of FETS and inductor value (2.4nH) for 180nm tech given in that paper
mosfet W/L ratio is cal by keeping L as 45nm
my question is how to scale inductor value for 45 nm tech
thanks in advance

Click to expand...

Hi Venkateshjuturu,
if you make such a large step from 180nm to 45nm, then keeping the biasing by keeping W/L constant may give you a good starting point but not the optimum design. The technologies are just too different.
We make software to solve such problems of full custom design migration (MunEDA SPT). In a first step, the schematic is converted by pre-defined rules, which usually include keeping R, C, L (inductance), and W/L ratio constant. The results for VCOs are usually functional and OK as an initial design, but not optimal. Therefore we need a second step, using our multi-objective circuit optimizer with a simulator to fine tune the device parameters, so that the circuit has good performance, low power consumption, low noise and low sensitivity to process variation and mismatch. If your target technology is TSMC, you may want to look into the 65nm RF RDK, there's a tutorial for our sizing software.
Regards,
Michael