karthik.venkata2020
Newbie level 4
i am doing my MS project in physical design domain , i was supposed to design a buffer cell .Can any body tell me what are the basic to be known for designing clock buffer ?
Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
M.S., I presume means master of science.
The post would make sense in the Analog IC Design or possibly ASIC Forum.
Hi Karthik,
Actually clock buffers are predefined in libraries. During P&R flow, we just link that libraries. I guess you have to design a library for Clock Buffer which has equal rise time fall times with different drive strength.
Thanks,
Alam