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What to consider when writing VHDL codes for Altera devices?

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Nidhi gupta

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Synthesis using altera

My design consists of many FSMs interacting with each other.What factors we should consider while writing vhdl code for Altera devices so as to optimise the design
also, is it possible to use vhdl testbench file instead of scf file.


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/pisoiu
 

Synthesis using @ltera

for coding styles for fsm's please refer to the book by ben cohen.It clearly mentions the guidelines for coding for synthesis.if u are trying to code ur fsm as a mealy or moore machine,first separate the code into combinational and sequential blocks(when u synthesize the design u will see the state register and combintorial block clearly in your design,without any ambiguity).do not use variables inside clocked processes ,(they will infer latches,to avoid assign initial values to variables).These are generallized guidelines for synthesis.,for more u can refer to the book.

regards
amarnath
 

Re: Synthesis using altera

Hi Nidhi

I think u can use "One Hot Encoding" in ur state machines, it can optimize the synthesis results.

Regards

Jaspreet Singh
 

Synthesis using @ltera

ben cohen's book is quite good!!!
 

Re: Synthesis using altera

well, though it can optimise the design(one-hot) is it not a lengthy and use a large number of flip flops, well using mealy gives u a perfect idea on what u r doing.
 

Re: Synthesis using altera

If the FSM has less states then you can use binary coding for them i.e. "000" "001" 010" "011" ..... "111".
If the states are more than 7 then go for one-hot.
 

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