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Amplifier design....Help!

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kart339

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Hi folks,
I'm a grad student new to Analog design. Am working on my first project which is an amplifier with the specs as follows:

Vdd - 1V
Pow: 80uW
BW: 10MHz
0.35u TSMC process
Phase margin: 60
Gain=60 dB

Any ideas on how I should go about this design......type of amp I should use, how many stages, how to meet the phase margin and gain reqs....your help highly appreciated. Thanks in advance people!
Kart
 

the gain is moderate so you can do this design with 2 stage opamp. Use Nulling resistor to do compensation using transistor in triode mode. If you want step by step example, go to www.aicdesign.org and look at P Ellen's lecture notes. This project is very do-able and won't take you long to design. Layout is another game, it comes with practice. Good luck.
 

Thank you Chinito! Will do as you say...it will be a transistor level design though, guess I will use the diff amp ckts for the op amp....Thanks again
Kart
 

Are you sure about 1V power supply for 0.35u CMOS?? It seems quite problematic.. What's the usual value for Vt of MOS in this technology?
 

I agree, 1 V supply is little too low for .35 um technology. Ideally, it should be at least 1.3V according to scaling rule.

Added after 3 minutes:

first stage, diff amp
second stage, common source
in between compensation circuitry made of Cc and Rc where Cc is compensation capacitor and Rc is the compensation/nulling resistor implemented using NMOS (or PMOS depending on what's your input transistor type) in triode region.
 

Thanks for responding chinito, borodenkov ......Vt for PMOS is -0.77 V, 0.57V for NMOS for 0.35u TSMC process. Anyway will try the diff amp- CS config and let u guys know how it goes.....
 

Imho, if this is your 1st project - the task is too difficult. It might be possible to make a design according to your spec (I've seen an IEEE paper about 0.5u CMOS OTA with 1V power supply, 40uW power dissipation, 2 MHz bw, 60 dB gain and 60 degrees phase margin), but for sure you'll have to use special low-voltage design techniques (bulk-driven designs etc)..
 

I checked a couple of IEEE papers for similar specs and came across a couple...Thanks for the idea Brodenkov. And apparently you can achieve the specs using a diff amp input and CS output stage (appreciate your idea Chinito) with the right transistor sizing and biasing. Someone did it the previous semester at school.....
 

the Vt is 0.7
design a 1V opamp
how to?
I think you can not
 

I think u should try design it with 2V Vdd.
 

the minimum supply must be atleast equal to vtn+vtp in the gate driven circuits
 

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