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[SOLVED] Power up and Initialization sequence for a design.

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anonymous.

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How to create/synthesize a power up sequence for a specific design?

Let's take for example a DDR3 memory controller. Power up or Reset initialization sequence requires asserting/deasserting multiple signals, each for a specific amount of time or requires that some signals become asserted a specific amount of time before other signals, and so on.

How is this done in hardware? and how can it transfer control to normal logic after finishing the required sequence? and how to write a synthesizable VHDL code for something like this? I could use wait keyword bus this is not synthesizable. any help?
 

I guess you already realized that a DDR controller is a synchronous circuit driven by one or possibly multiple PLL generated clocks.

Think of a reset signal and everything else implemented in synchronous logic.
 

there is usually a POR analog module which generate a reset signal, and a clock analog module to provide the clock system, and after that the digital could wake-up properly and your state machine will de/assert your signals.
if you could not have the reset & clock, used a extenal sources through pads.
 
This is very simple timer logic, power up 500us, reset 200us, and the cke....
If you want to make generic/programmable logic to control such process, you have to write several timers/counter to do it.

anonymous. said:
How to create/synthesize a power up sequence for a specific design?

Let's take for example a DDR3 memory controller. Power up or Reset initialization sequence requires asserting/deasserting multiple signals, each for a specific amount of time or requires that some signals become asserted a specific amount of time before other signals, and so on.

How is this done in hardware? and how can it transfer control to normal logic after finishing the required sequence? and how to write a synthesizable VHDL code for something like this? I could use wait keyword bus this is not synthesizable. any help?
Click to expand...
 

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