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What will be the biasing voltage for PMOS acting in saturation region?

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Hai everyone,
I have a doubt in biasing a PMOS transistor. For a PMOS transistor, the condition for saturation region is Vgs < Vt and Vds < Vgs - Vt. If Vds is 0.6 V, Vt is -0.2 V, then what should be the Vgs ? as per the condition, it should be negative. if we apply negative voltage, then how the second condition will be satisfied??
What will be the biasing voltage for PMOS acting in saturation region?

Thanks for your response in advance :)
 

For a PMOS just consider all the things as negative.

in your case you mention Vds as 0.6V. This would mean that Drain is 0.6V higher than Source. This would be incorrect for a PMOS.

What you mean to say is Vsd = 0.6V =>
Vds = -0.6V
Vth = -0.2V

Therefore, Vds + Vth < Vgs < Vth
i.e.
-0.8V < Vgs < -0.2V would make sure that the pMOS transistor is in saturation.
 
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Thank you for your reply sir, ..

In many LNA design papers, Vgs of PMOS is connected to ground . can you tell me the reason for that?
 

When you say that Vgs of PMOS is connected to ground, what do you mean??

Is the Gate connected to ground or the source connected to ground or both?
 

nitishn5 said:
When you say that Vgs of PMOS is connected to ground, what do you mean??

Is the Gate connected to ground or the source connected to ground or both?
Click to expand...

Gate is connected to ground...
if the gate is connected to gnd, how PMOS is acting in saturation region?
 

If you have the Gate and Drain of a PMOS grounded and the source at a higher voltage, then it is just a diode connected PMOS which would be in saturation.

If the voltages satisfy the conditions for saturation then it would be in saturation, no matter whether the gate is grounded or not.
 

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