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[SOLVED] Signal cannot be synthesized, bad synchronous description.

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nakshathra

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the following code results the below error on synthesis:
ERROR:Xst:827 - "C:/Documents and Settings/Administrator/Desktop/xilinx prgms/sqr/sqr.vhd" line 65: Signal clkout cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Please resolve the error.

Code: 
process(reset,clk_count(25))
begin
if reset='1' then
	count<=x"0000";
	clkout<='0';
elsif (clk_count(25)='1' and clk_count(25)'event) then
	count<=count+'1';
	clkout<='1';
else clkout<='0';
end if;
end process;
 

nakshathra said:
the following code results the below error on synthesis:
ERROR:Xst:827 - "C:/Documents and Settings/Administrator/Desktop/xilinx prgms/sqr/sqr.vhd" line 65: Signal clkout cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

Please resolve the error.

Code: 
process(reset,clk_count(25))
begin
if reset='1' then
	count<=x"0000";
	clkout<='0';
elsif (clk_count(25)='1' and clk_count(25)'event) then
	count<=count+'1';
	clkout<='1';
else clkout<='0';
end if;
end process;
Click to expand...

this is not a standard way to implement a sequential process.
(the last "else" branch with the clkout tie to '0').
so clkout logic does not make much sense.
also you are implementing a sort of a riple counter here which is problematic issue.
in general, you must stick to a synchronous design with one clock,
as much as possible.
even async reset can be avoided by a synchroniser circuit.

hope i helped...
 

I think the problem is the "else clkout<='0';". Because "clk_count(25)'event" is an instant in time (ideally) then your else statement implies every other point in time "clkout<='0'". So your your asking it to create a perfect impulse like: _____|______ which it can't do of course. If you want a really short pulse at the rising edge of clk_count(25) then you need to explicitly state that, for example, with NOT and XOR gates: https://vhdlguru.blogspot.ca/2010/04/combinatorial-frequency-multiplier.html

If you want your "clkout" signal to remember its state after "clk_count(25)'event" then use the usual async reset syntax:

Code: 
if reset = '1' then
    clkout<='0';
else
    if (clk_count(25)='1' and clk_count(25)'event) then
        clkout <= '1';
    end if;
end if;
 

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