STA- Timing path from fast clock to slow clock

hello all,

i have doubt regarding, how all data from fast clock to slow clock path recivced correctly at capture flop?

suppose clock period of fast clock = 10ns and slow clock = 25ns then in that case launch clock is fast clock and capture clock is slow clock.

i think data of some edges from launch clock may not captured by capture clock? is that right?

If is there any method to handle this case? then please suggest.


for slow clock to fast clock path, we can consider multicycle path case so that there is no chance for data loss but here in case of fast clock to slow clock path, i'm little bit confused. how this path handled without data loss..?


thank you..

if you donot want to loose the data from fast clock to slow clock we need to meet timing in most strict case.
with above example if you expand clock for some cycles, the lauch will be at x and capture wil be at x+5 so you need to meet timing for 5 ns

Hai ramesh

you can set multicycle path for both the conditions i.e from slow clock to fast clock and from fast clock to slow clock
for the condition from slow clock to fast clock
set_multicycle_path x -setup -from launch_clk(slow) -to capture_clock(fast) -end ---> which will add multicycle to the capture clock

for the condition from fast clock to slow clock
set_multicycle_path x -setup -from launch_clk(slow) -to capture_clock(fast) -start -----> which will add multicycle to the launch clock

thank you.

vimalraj205 said:

Hai ramesh

you can set multicycle path for both the conditions i.e from slow clock to fast clock and from fast clock to slow clock
for the condition from slow clock to fast clock
set_multicycle_path x -setup -from launch_clk(slow) -to capture_clock(fast) -end ---> which will add multicycle to the capture clock

for the condition from fast clock to slow clock
set_multicycle_path x -setup -from launch_clk(slow) -to capture_clock(fast) -start -----> which will add multicycle to the launch clock

thank you.

Click to expand...

hi vimalraj,

Thank you for reply..

you means that by mentioning set_multicycle_path for both the case is the solution to this problem..

for fast to slow clock => due to argument "-start" --> which will add multicycle to launch clock.. ok..but about one thing i still have confusion..means in that case no need to check setup violation for each and every launch clock edge..as we adding multicycle to launch clock.

can you give detail idea about what actually happen while domain crossing for fast clock to slow clock..?


Thank you.

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mail4idle2 said:

if you donot want to loose the data from fast clock to slow clock we need to meet timing in most strict case.
with above example if you expand clock for some cycles, the lauch will be at x and capture wil be at x+5 so you need to meet timing for 5 ns

Click to expand...

hi mail4idle2,

the lauch will be at x and capture wil be at x+5 so you need to meet timing for 5 ns. ok this is right.

but what about launch edge appearing x-10..for this edge capture also at x+5..

in that case i want to know that how can both launch clock edge(consider 1st and 2nd) captured at capture clock edge..? or only nearest launch clock edge(2nd edge) data only captured and transfered..? then what about data occured at 1st clock edge?

thank you.

hai Ramesh

yes rightly said

you can search Multicycle path for multiple clock domains and find some useful docs regarding this

thank you