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    which one is mostly preferable in between ?: and if else in verilog design

    In verilog design, we have ?: operator and if..else statement.

    for ex: c = foo ? a:b
    for ex: if (foo)
    c = a;
    else
    c = b;

    which one of the above code is preferable in verilog design prospective

    - - - Updated - - -

    and what is the difference between them.

    Shall i use ?: operator in design rather than if..else . If Yes, why?

    •   Alt22nd October 2013, 06:14

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    Re: which one is mostly preferable in between ?: and if else in verilog design

    ?: operator is mainly used for comparisons and it is well suited for small statements.

    If the statement you like to print is large or if you are in need checking multiple conditions, you have to go for if..else..
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    Re: which one is mostly preferable in between ?: and if else in verilog design

    Hello,

    In this scenario :
    If we use ?: operator, than during synthesis - what is hardware?

    If we use If, else loop , than during synthesis - what is hardware?

    Thanks in advance.



    •   Alt22nd October 2013, 07:49

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    Re: which one is mostly preferable in between ?: and if else in verilog design

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    •   Alt22nd October 2013, 08:06

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    Re: which one is mostly preferable in between ?: and if else in verilog design

    Hello,
    Thanks. I am interested to know that what is the hardware of above 2 scenario?



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    Re: which one is mostly preferable in between ?: and if else in verilog design

    Hi,

    as far as I know the hardware will depend on many things. For instance, on the cells library and on the constraints file which are both inputs to the logic synthesizer.

    However, my guess is that both "? :" and "if else" will generate the same hardware if they are synthesized with the same .lib and .sdc files.

    In a high-level, it would be a simple MUX.



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    Re: which one is mostly preferable in between ?: and if else in verilog design

    As far as synthesis to hardware, there is no functional difference between the conditional operator and the if/else statement. The conditional operator can be nested in other expression so that you do not need intermediate variables, so it is more compact. However, that can make it more difficult for others to read your code. SystemVerilog add a few additional flavors of if statements (unique-if/priority-if)that can influence how the if statement gets optimized.

    There is a difference between the two constructs when it comes to X-propagation in logic simulation, specifically the case where 'foo' is unknown. The subject of X-propagation during dynamic simulation is a deeply technical and controversial subject. Just search for 'Verilog X-propagation'
    Dave Rich
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    2 members found this post helpful.

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    Re: which one is mostly preferable in between ?: and if else in verilog design

    OK. Thanks I got it.

    But I have another doubt for mux as you talked about X-propagation.

    S A0 A1 o/p
    1) X 0 0 0 -- no doubt as schematic is also working as per truth table
    2) X 1 1 1 -- Doubt : As hardware perspective, S=X means S=1 or S=0, in both case the output is 1.
    But in simulation if we check it through the gate level of mux than output is X but hardware perspective it is 1. So is there any specific reason why this happens? or how can we prove it for simulation?

    Thanks in advance.

    -Maulin Sheth



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    Re: which one is mostly preferable in between ?: and if else in verilog design

    Not sure, but I came up with this:

    From the truth table, we got:

    OUT = (~S).A + S.B

    If A = 0 and B = 0, we got:

    OUT = (~X).0 + X.0 = 0 + 0 = 0

    But if A = 1 and B = 1, we got:

    OUT = (~X).1 + X.1 = X + X = X

    - - - Updated - - -

    Also, note that:


    ~x = x
    0&x = 0
    1&x = x&x = x
    1|x = 1
    0|x = x|x = x
    0^x = 1^x = x^x = x
    0^~x = 1^~x = x^~x = x



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    Re: which one is mostly preferable in between ?: and if else in verilog design

    Maulin,

    As Liffs points out, there is only one representation of X in a Verilog (or VHDL) simulation. You really need some sort of formal analysis so that when an X value re-converges, you know that the two X's in your equation are identical values, even though you do not know its value.
    Dave Rich
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    Mentor Graphics Corporation



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    Re: which one is mostly preferable in between ?: and if else in verilog design

    I got it.
    Thanks a lot.



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