dft123
Junior Member level 1
Hi,
I am using Synopsys DC/DFTC to insert scan at IP level.
I have 2 clocks at the IP ports: CLK and TST_CLK. The PLL sits outside the IP and CLK is assumed to be PLL clock. TST_CLK is the shift clock. Both these clocks goes into a CKGEN block (kind of OCC in RTL) where one single internal clock CCLK comes out. This act as the shift clock during shift and also the at-speed clock during capture and is routed to all scanable flops in the design.
What is the best way to define this clocking to DFTC during scan insertion?
I am using Synopsys DC/DFTC to insert scan at IP level.
I have 2 clocks at the IP ports: CLK and TST_CLK. The PLL sits outside the IP and CLK is assumed to be PLL clock. TST_CLK is the shift clock. Both these clocks goes into a CKGEN block (kind of OCC in RTL) where one single internal clock CCLK comes out. This act as the shift clock during shift and also the at-speed clock during capture and is routed to all scanable flops in the design.
What is the best way to define this clocking to DFTC during scan insertion?