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How can we detect false-paths at RTL level?

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er.akhilkumar

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Hello All,

There are methods to detect false-path by using SAT test-vector generation. But is this method used at RTL level? I think at RTL level while doing verification code coverage can also help in detecting false paths.

Regards,
Akhil
 

false path should be provided by the designers.
 

Let me put it another way. If an engineer designs a circuit and can't tell what is and isn't a false path, then they shouldn't be allowed to design something unsupervised.

e.g. the first register of a clock domain crossing synchronizer has a false path from the launch register in the asynchronous clock domain to the first register in the synchronizer. This is a false path because we expect the path to not meet any timing constraints.

Regards
 

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