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how to use BUFGDLL of Xilinx FPGA? help!!!

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bufgdll

how to use bufgdll of Spartan2 fpga ?
my design includes a Top module which will call some small module and some other modules.

when i use

u1: bufgdll(clk_in,clk) ;

there errors !!!

how to use BUFGDLL ?
thanks!
 

xilinx bufgdll spartan

vvsvv said:
how to use bufgdll of Spartan2 fpga ?
when i use

u1: bufgdll(clk_in,clk) ;

there errors !!!

how to use BUFGDLL ?
thanks!
Click to expand...

First of all: how do you expect to get an answer if you don't post the error?

Secondly: have you read the Xilinx Application Note "Using the Virtex Delay-Locked Loop XAPP132"? Go to support.xilinx.com to find it.
 

Which HDL are you using?

In VHDL, you include the Xilinx library (uncomment it), and use component instantiation:
Code: 
u1: bufgdll port map(
    I => clk_in,
    O => clk
  );
 

Check out that clk_in is not driven by an IBUF or IBUFG, clkin here can not be driven by input buffers "got it"
 

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