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Doubt in guard ring details..

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vinodhsaminathan

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Hi
I am doing analog layout, am confused with metal width present in guard ring. s there any factors we have to consider while choosing width.
i thought it s fixed size, n little more than minimum width we have to choose. pls clear it.

thx
 

What kind of guard ring do you mean? If it is only used to avoid latch up, i think there is no special rule for the width, because it is just a pick up function. If it is also used as the current path of ESD, it should be as wide as possible.
 

Hi
I have matched PMOS transistors and i have enclosed it with a N-well guard ring.can u explain briefly abt ESD current path.

Thx
 

vinodhsaminathan said:
... PMOS transistors ... enclosed with a N-well guard ring.
Click to expand...

In this case the N-well guard ring is the bulk contact of the PMOS transistors (to be connected to VDD or to the PMOS sources). Minimum metal width is enough. Has nothing in common with ESD.
 

Hi,
What is ESD current path and how guard ring is used to carry it. pls explain
 

If the PMOS or NMOS is used as ESD buffer, then you should make the source metal connection, which is connected to VDD or ground, as wide as possible.
 

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