party-pansen
Newbie level 3
Hi,
after running RTL Compiler I get a verilog netlist without vdd! and vss! ports. I think the reason is the .lib library that does not provide them for the standard cells. (but they are declared in .lef). Im not sure if this is a problem or not...
When running Encounter after init_design I do the following:
(Power pins are initialized by "set init_pwr_net "vdd"" and "set init_gnd_net "vss"")
1. Creating power stripes:
2. Placing design and Connecting stdcelll vdd!, vss! pin to vdd vss :
3. Then I Use the sroute command to create power rails for each standard cell row and connect them to the stripes:
The logfile then gives me many: "Port at (xxxx yyyy) : Not routed because of unknown reason."
This position for example is one of the created power rails that IS connected to a power stripe with vdd/vss pin
The "verifyConnectivity -noUnroutedNet" command gives me:
The markers are created around my design boundary on almost every vdd/vss!
I'm not sure how to handle this problem, or maybe I can even ignore it!? But what am I doing wrong? Why are the power pins/nets not connected correctly?
thanks for your advice!
party-pansen
after running RTL Compiler I get a verilog netlist without vdd! and vss! ports. I think the reason is the .lib library that does not provide them for the standard cells. (but they are declared in .lef). Im not sure if this is a problem or not...
When running Encounter after init_design I do the following:
(Power pins are initialized by "set init_pwr_net "vdd"" and "set init_gnd_net "vss"")
1. Creating power stripes:
Code:
addStripe \
-max_same_layer_jog_length 2 \
-padcore_ring_bottom_layer_limit metal1 \
-padcore_ring_top_layer_limit metal3 \
-set_to_set_distance ${_powdistance} \
-spacing ${_powerstripespacing} \
-xleft_offset ${_xpoweroffset} \
-layer metal2 \
-width ${_powerstripewidth} \
-nets {vss vdd} \
-extend_to design_boundary \
-create_pins 1 \
-pin_layer metal2 \
-over_pins 02. Placing design and Connecting stdcelll vdd!, vss! pin to vdd vss :
Code:
placeDesign
addTieHiLo -cell {vddcon vsscon}
scanReorder -scanEffort high -preferV true
globalNetConnect vdd -type pgpin -pin vdd! -inst *
globalNetConnect vss -type pgpin -pin vss! -inst *
applyGlobalNets3. Then I Use the sroute command to create power rails for each standard cell row and connect them to the stripes:
Code:
sroute -allowLayerChange 0 \
-detailed_log \
-nets {vss vdd} \
-straightConnections straightWithDRCCleanThe logfile then gives me many: "Port at (xxxx yyyy) : Not routed because of unknown reason."
This position for example is one of the created power rails that IS connected to a power stripe with vdd/vss pin
The "verifyConnectivity -noUnroutedNet" command gives me:
The markers are created around my design boundary on almost every vdd/vss!
I'm not sure how to handle this problem, or maybe I can even ignore it!? But what am I doing wrong? Why are the power pins/nets not connected correctly?
thanks for your advice!
party-pansen
