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The best solution is to use ROD like uladz55 said.
ROD = Relativ Object Design.
More details in Cadence openbook, Virtuoso layout editor section, ROD subsection.
With ROD, you draw one "patern" which will be "multiplied" in the direction you'll stretch.
You will define the patern and the stretch rules.
Is very simple, and you can save it like xxx.il file (skill) and to load it when you need.
With the tutorial in front of you, you will do this in 30 min.
Thanks for the responses.
I've finished the guard ring using multipath and ROD objects but I think I haven't done it well because LVS tells me that MOS and bipolar transistors' substrates are connected to the same net.
In my design, I've used different nets for power and ground. So it's draw on the schematic view but the LVS says that ground nets are not well isolated. I've put a guard ring around the MOS-section. And this guard ring is connected to ground (VSS) as well as NMOS substrates are. PMOS substrates are connected to power (VDD). On the other hand, I've connected BJT substrates to ground (VTT). Bipolar power is VCC.
Any solution?
it should not hapen that u forward bias any diodes
see
pmos substrate is connected to positive supply and if u put a p+ gaurd ring around it connect it to the most -ve supply
for nmos the reverse will be true that is the substrate ring is connected to the most -ve supply and n=gaurd ring to the +ve supply
with respect to the above tthe above the bipolar gaurd ring should not be forward biased
if ur kit has erc rules please run them and see any voilation other wise ur chip will emit smoke when is is connected to supplys
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